Analogue to digital converters

ABSTRACT

In an integrating analogue-to-digital converter, particularly a digital voltmeter, the input voltage is applied to an integrator for a sampling period equal to one period of the local line frequency (e.g., 50 Hz or 60 Hz). The integrator has a transfer function of the form 1/pT for a fixed period S just less than the minimum possible duration of the sampling period, and of the form 1/(1+pT) for the remainder dS of the sampling period. Thus D.C. voltages are integrated for a known fixed period, while normal mode interference at the local line frequency is integrated out.

United States Patent 1 1 [111 3,729,733 Dorey 51 K51? 24, 1973 [s41ANALOGUE T DIGITAL 3,566,265 2 1971 Reid ..340/347 NT CONVERTERS3,569,957 3/1971 Masterson ..340/347 NT [75] Inventor: Howard AnthonyDorey, Godalm- FOREIGN PATENTS OR APPLICATIONS Surrey England 1,153,2015/1969 Great Britain ..340 347 NT [73] Assignee: The Solatron ElectronicGroup Farnborough Hampshire Primary Examiner-Charles Mlllel' EnglandAttorney-William R. Sherman et a].

[21] Appl- 201,553 in an integrating analogue-to-digital converter,particularly a digital voltmeter, the input voltage is ap- ForeignApplication Priority Data plied to an integrator for a sampling periodequal to one period of the local line frequency (e.g., Hz or NOV. 24,Great Britain The integrator has a transfer function of the form l/pTfor a fixed period S just less than the C 340/347 324/99 D minimumpossible duration of the sampling period, [51] Int. Cl; ..H03I( 13/20and of the form l/(1+pT) for the remainder d8 of the [58] Field ofSearch ..340/347 NT, 347 AD; sampling period. Thus D.C. voltages areintegrated for 324/99 D; 235/ 183 a known fixed period, while normalmode interference at the local line frequency is integrated out. R fC'ted [56] e erences 7 Claims, 2 Drawing Figures UNITED STATES PATENTS3,439,271 4/1969 Metcalf et a]. ..340/347 NT MPARATOR orcour 30/ CLOCK Roscumon so 28/ a 7 HI w s m W "3. l 1 "P l 50 SCHMITT Ii, 1 TRIGGER 2 IJ l/ M 2 Sheets-Sheet 2 l l l l I SAMPLING INTERVAL lmcmslrg] 5 S)INTERVAL ANALOGUE T DIGITAL CONVERTERS The present invention relates tointegrating analogue to digital converters of the kind wherein, in eachconversion period, an input electrical signal to be converted is appliedto an integrating means during a sampling interval to tend to cause theoutput of the integrating means to ramp away from a datum level, and areference signal is applied to the integrating means during a digitizinginterval in such a manner as to restore the output of the integratingmeans to the datum level, the ratio of the lengths of the digitizinginterval to the sampling interval being dependent upon the meanmagnitude of the input signal during the sampling interval. Typically,clock pulses are counted during the digitizing interval to provide adigital measure vof the input signal. The reference signal may besubstituted for, or superimposed on, the input signal, and thedigitizing interval can follow, or occur during, the sampling interval.Such converters will hereinafter be referred to as converters of thekind described and typical examples are disclosed in the specificationsof British Patents No. 1,090,047, 869,262 and 1,220,091 (U.S. PatentsNo. 3,316,547, 3,051,939 and Application Ser. No. 764,490 filed Oct. 2,I968 respectively). One use of such a converter is as a digitalvoltmeter.

Integrating analogue to digital converters are specially useful whenconverting an analogue input signal contaminated with normal (series)made interference. Most normal mode interference, which appears inseries with the signal to be converted, can be attributed toline-frequency hum at 50I-Iz (and its harmonics) and may be reducedsignificantly by making the sampling interval equal to one or more lineperiods. Conventionally this is achieved by counting clock pulses fromthe start of the sampling interval and terminating the interval when thecount reaches a predetermined number. For example, the combination of alOOKHz clock oscillator arranged to feed clock pulses to a counter couldbe used to terminate the sampling interval when the count reached20,000, to provide an interval of mSecs (one period of 50Hz linefrequency). By this technique a normal-mode rejection of 60dB is readilyachieved for a nominal 50I'Iz interfering signal.

The description will, for ease of explanation, hereinafter be restrictedto normal-mode interference at a line frequency of 50l-lz (or itsharmonics) although it will be realized that the interference can occurat, and the invention is applicable to, frequencies other than linefrequency. Any small variations in the line frequency signal will resultin imperfect integration (or averaging) of the signal with a consequentreduction in the normal-mode rejection of the converter. For example, ai change in line frequency could reducethe normal-mode rejection toabout 40dB. The effects of such variations in line frequency on thenormal-mode rejection may be alleviated by varying the frequency of theclock oscillator in dependence upon that of the line frequency, and oneway of achieving this is disclosed in the specification of our BritishPat. application No. 41428/67 (Ser. No. l,245,578).

The present invention provides another way of alleviating the affects ofsmall variations in a normalmode interfering signal on the normal-moderejection of an integrating analogue to digital converter.

According to the present invention there is provided an analogue todigital converter of the kind described wherein an analogue inputelectrical signal is applied to an integrating means for a samplinginterval, S +dS, in each conversion period, and the integrating means isarranged to have a transfer function of the form l/pT, for apredetermined period S from the start of each sampling interval and atransfer function of the form I/( l pT for the remainder of the interval:18. T is the time constant of the integrating means and p is thedifferential operator d/dt. The sampling interval, S dS, is made equalto an integral number of periods, P, of the normal-mode interferingsignal to be rejected. If the period P of the interfering signal isconstant then dS remains constant but if P changes by i dP then dSchanges by i dP.

In a preferred embodiment of the invention T is made substantially equalto S which is defined as a number of cycles of an internal clock.

The invention will now be described by way of example with reference tothe accompanying drawings, in which:

FIG. I is a block schematic diagram of a dual-ramp digital voltmeterembodying the invention, and

FIG. 2 is a explanatory waveform showing the output level of theintegrating circuit during a measurement period.

In FIG. 1 the switches are shown as mechanical switches although inpractice they would probably be semi-conductor switches such as fieldeffect transistors.

Referring to FIG. 1, the voltmeter has an input terminal 10 to which avoltage to be measured may, in operation, be applied. It is assumed thatthe input voltage is subjected to normal-mode interference at the SOl-izline frequency. The terminal 10 is coupled through a switch 12 to theinput of an integrating circuit 14 comprising an operational amplifier16, an input resistor 18 and a feed-back capacitor 20 connected betweenthe input and the output of the amplifier 16. In this configuration theintegrating circuit 14 has a transfer function of the form l/pT- whereT, is the time constant of the resistance R, of the resistor 18 and thecapacitance C of the capacitor 20. Also connected between the inputandoutput of amplifier 16 is a series circuit comprising a resistor 21and a normally-open switch 23. When the switch 23 is closed the circuit14 has a transfer function of the form l/(l pT where T is the timeconstant of the resistance R of the resistor 21 and the capacitance C ofthe capacitor 20.

A source 24 of a reference voltage of opposite polarity to that of theinput voltage is coupled through a switch 26 to the input of the circuit14. s

The switches 12 and 26 are controlled by bistable flip-flop circuits 28and 30 respectively, each switch being closed when its respectiveflip-flop is set. 7

Connected to the output of the integrating circuit 14 is a comparator 32which is arranged to provide a reset signal to the flip-flop 30 eachtime the output level of the circuit 14 returns to a datum level (inthis case signal ground).

puts connected to the outputs of the flip-flops 28 and 30. Thus a lappears on the output of the OR gate 40 whenever either one of theswitches 12 and 26 is closed, to open the AND gate 36 and allow clockpulses to be counted by the counter 38.

The counter 38 has a full-house count of 20,000. When the counterreaches 20,000 it provides a pulse to set the bistable flip-flop circuit41. When in the set state the flip-flop 41 closes switch 23 and inhibitsthe passage of clock pulses through the AND gate 36.

The operation of the digital voltmeter is controlled by a timing controlcircuit, shown within the broken line 44. The circuit 44 comprises aSchmidt trigger 46 coupled to receive a signal at the 50l-lz linefrequency and provide a 50l-lz square wave to a divide by two circuit48, which provides at its output a 25Hz square wave (that is mSecscontrol pulses). The control pulses are used to control the operation ofthe voltmeter. It will be realized that the line frequency has only anominal value of SOl-lz and will be subject to slight variations infrequency about this nominal value.

It will be assumed that positive'going edges are used to set and resetthe flip-flops.

A positive-going edge of a control pulse from the circuit 48 is appliedto reset to zero the counter 38 and after a suitable delay provided by adelay circuit 50 the flip-flop 28 is set to close the switch 12 and openAND gate 36 by way of the OR gate 40.

When switch 12 closes (at time I,,, FIG. 2) the input voltage is appliedto the integrating circuit 14 and the output level of the integratorramps away from a datum level, which is in this case signal ground.lOSKl-lz clock pulses are counted by counter 38 until the count reachesa full house of 20,000 when the flip-flop 40 is set to inhibit AND gate36 thereby preventing the further passage of clock pulses, and close theswitch 23 to change the transfer function of'the circuit 14 to the forml/(l +pT where T is the time constant of the resistance R of resistor 21and the capacitance C of capacitor 20. This occurs after about l9mSecs(time t,) which is assumed to be less than the minimum period of onecycle of the line frequency.

' The switch 12 remains closed until the end of the control pulse(approximately 20mSecs) when the negative-going edge of the pulse isinverted by an inverter 52 and applied to reset the flip-flop 28 andthereby open switch 12 at time t Thus the sampling interval S dS duringwhich the input voltage is applied to circuit 14 is made equal to oneperiod of the line frequency which may vary, but

the interval S(t,, to t,) when the circuit 14 has a transfer.

function l/pT is maintained constant. The interval 118 between time t,to t, varies with variations in line frequency.

The positive-going output of inverter 52 is also applied to reset theflip-flop 41 which removes the inhibit signal from AND gate 36 and opensswitch 23 causing the transfer function of the circuit 14 to revert tothe form l/pT,, and to set the flip-flop 30 thereby closing switch 26 toapply the reference voltage to the integrating circuit 14. The output ofthe circuit 14 ramps back towards datum level and when it reaches datum,at time the comparator circuit 32 causes the flip-flop 30 to reset thusopening'switch 26 and closing AND gate 36. The number N of clock pulsescounted by the counter 38 during the digitizing interval t to is ameasure of the magnitude of the input voltage applied during the periodt, to t At the end of the digitizing interval the number of clock pulsesin the counter 38 is decoded in a decoder 56 and displayed on a display58.

Considering a steady d.c. input voltage V,. After the period t=0 to tthat is S, the output level Between t, and t the V0 remainssubstantially constant and the equation applies.

To avoid discontinuities of the output level V,,, equa- A tions 1 and 2must be equal:

(VI/R1) /C)= 1'( 2/ 1) S CR T Therefore the time constant of theintegrating means when it has the form 1/(1 pT should equal the periodS.

Thus d.c. voltages are measured as if the switch 12' were closed for afixed interval S but a.c. voltages are integrated for the period (S dS)and in the embodiment normal-mode interference will be substantiallyless than it would have been if it had been integrated for the intervalS only. If the period P of the line voltage changes by i dP then the dc.input voltage will still be integrated for the same fixed period but thea.c. voltage will be integrated for the period (S dS i dP) ensuring goodnormal-mode rejection of the a.c. signal.

A.C. Voltages are measured as though they were integrated in theinterval (S dS) to an accuracy of (dS/S)". Thus ifS differs from (S +dS)by 1 percent the resultant error is 0.01 percent.

If the voltmeter is measuring an a.c. voltage and the wave form isrectified, but not smoothed, before being applied to the integratingmeans this form of integration may be used to measure the mean value ofa whole number of cycles of the wave form. Known voltmeters take a longsettling period as a complex filter is required.

What is claimed is:

1. An analogue to digital converter for converting to digital form ananalogue input signal which input signal may be subject to a normal modeinterfering signal of period P, the converter comprising integratingmeans having an input and an output, timing means for applying the inputsignal to the input of the integrating means for a sampling interval S(15 to cause the output level of the integrating means to deviate from adatum level, a source of a reference signal, a source of clock pulses, apulse counter, means for applying the reference signal to the inputofthe integrating means in such a manner as to cause the integratingmeans output to return to the datum level during a digitizing intervaland for simultaneously causing the pulse counter to count clock pulses,and means responsive to the return to the integrating means output levelto the datum level for terminating the digitizing interval, theintegrating means having first and second selectable transfer functionsof the form l/pT and l/(l pT respectively, wherein T and T arepreselected time constants and p is the differential operator d/dt, andcontrol means for selectively causing the integrating means to have atransfer function of the first form during the digitizing interval andduring a predetermined period S from the start of each samplinginterval, and a transfer function of the second form during theremaining period of the sampling interval.

2. A converter according to claim 1, wherein the timing means includesmeans responsive to the interfering signal of period P for causing thesampling interval S 418 to be substantially equal to an integral numberN of periods P.

3. A converter according to claim 2, where N is equal to unity.

4. A converter according to claim 1, wherein the time constant T, of thesecond transfer function is substantially equal to the period S.

5. A converter according to claim 2, wherein the timing means furtherincludes means for inhibiting the counting of clock pulses during theperiod dS.

6. A converter according to claim 1, wherein the integrating meansincludes a circuit comprising a capacitor, and a series circuit of aresistor and switch meanscoupled in parallel with the capacitor, theswitch means having first and second operative states wherein it issubstantially open-circuit and substantially short-circuit respectively,the control means being operably coupled to the switch means for causingthe integrating means to have transfer functions of the first and secondforms when the switch means is in one and the other of its operativestates respectively.

7. A converter according to claim 6, wherein the control means includesmeans for causing clock pulses to be counted by the counter during thesampling interval and means coupled to the counter to operate the switchmeans and thereby cause the integrating means to have a transferfunction of the second form when the count reaches a predetermined valuerepresentative of the period S.

1. An analogue to digital converter for converting to digital form ananalogue input signal which input signal may be subject to a normal modeinterfering signal of period P, the converter comprising integratingmeans having an input and an output, timing means for applying the inputsignal to the input of the integrating means for a sampling interval S +dS to cause the output level of the integrating means to deviate from adatum level, a source of a reference signal, a source of clock pulses, apulse counter, means for applying the reference signal to the input ofthe integrating means in such a manner as to cause the integrating meansoutput to return to the datum level during a digitizing interval and forsimultaneously causing the pulse counter to count clock pulses, andmeans responsive to the return to the integrating means output level tothe datum level for terminating the digitizing interval, the integratingmeans having first and second selectable transfer functions of the form1/pT1 and 1/(1 + pI2) respectively, wherein T1 and T2 are preselectedtime constants and p is the differential operator d/dt, and controlmeans for selectively causing the integrating means to have a transferfunction of the first form during the digitizing interval and during apredetermined period S from the start of each sampling interval, and atransfer function of the second form during the remaining period dS ofthe sampling interval.
 2. A converter according to claim 1, wherein thetiming means includes means responsIve to the interfering signal ofperiod P for causing the sampling interval S + dS to be substantiallyequal to an integral number N of periods P.
 3. A converter according toclaim 2, where N is equal to unity.
 4. A converter according to claim 1,wherein the time constant T2 of the second transfer function issubstantially equal to the period S.
 5. A converter according to claim2, wherein the timing means further includes means for inhibiting thecounting of clock pulses during the period dS.
 6. A converter accordingto claim 1, wherein the integrating means includes a circuit comprisinga capacitor, and a series circuit of a resistor and switch means coupledin parallel with the capacitor, the switch means having first and secondoperative states wherein it is substantially open-circuit andsubstantially short-circuit respectively, the control means beingoperably coupled to the switch means for causing the integrating meansto have transfer functions of the first and second forms when the switchmeans is in one and the other of its operative states respectively.
 7. Aconverter according to claim 6, wherein the control means includes meansfor causing clock pulses to be counted by the counter during thesampling interval and means coupled to the counter to operate the switchmeans and thereby cause the integrating means to have a transferfunction of the second form when the count reaches a predetermined valuerepresentative of the period S.